( go2.asm):00001 ******************************************************************************* ( go2.asm):00002 * TurbOS ( go2.asm):00003 ******************************************************************************* ( go2.asm):00004 * See LICENSE.txt for licensing information. ( go2.asm):00005 ******************************************************************** ( go2.asm):00006 * ( go2.asm):00007 * $Id$ ( go2.asm):00008 * ( go2.asm):00009 * Edt/Rev YYYY/MM/DD Modified by ( go2.asm):00010 * Comment ( go2.asm):00011 * ------------------------------------------------------------------ ( go2.asm):00012 * 1 2023/08/29 BGP ( go2.asm):00013 * Created. ( go2.asm):00014 ( go2.asm):00015 nam go ( go2.asm):00016 ttl Very simple initial program ( go2.asm):00017 ( go2.asm):00018 use defs.d ( defs.d):00001 * Assemble-time capability flags ( defs.d):00002 * ( defs.d):00003 * Feature Flags - eliminating one or more of these capabilities saves code space. ( defs.d):00004 * ( defs.d):00005 * Manage your own interrupts or install interrupt service routines using F$IRQ. 0000 ( defs.d):00006 _FF_IRQ_POLL equ 0 Set to 1 for interrupt service routine polling ( defs.d):00007 ( defs.d):00008 * Use virtual interrupt service routines using F$VIRQ. 0000 ( defs.d):00009 _FF_VIRQ_POLL equ 0 Set to 1 for virtual interrupt service routine polling ( defs.d):00010 ( defs.d):00011 * Wall time gives year/month/date/hour/minute/second support. 0000 ( defs.d):00012 _FF_WALLTIME equ 0 Set to 1 for a software wall time clock ( defs.d):00013 ( defs.d):00014 * Module CRC and header parity checks are useful for integrity, but slows down loading. 0000 ( defs.d):00015 _FF_MODCHECK equ 0 Set to 1 for module header and CRC checking ( defs.d):00016 ( defs.d):00017 * Unified I/O adds a standard device interface at the expense of more memory. 0000 ( defs.d):00018 _FF_UNIFIED_IO equ 0 Set to 1 for unified I/O ( defs.d):00019 ( defs.d):00020 * Booting from an external storage device can bring in additional functionality. 0001 ( defs.d):00021 _FF_BOOTING equ 1 Set to 1 for bootfile loading ( defs.d):00022 ( defs.d):00023 * TurbOS system definitions ( defs.d):00024 use turbos.d ( turbos.d):00001 ******************************************************************************* ( turbos.d):00002 * TurbOS ( turbos.d):00003 ******************************************************************************* ( turbos.d):00004 * See LICENSE.txt for licensing information. ( turbos.d):00005 ******************************************************************************* ( turbos.d):00006 * ( turbos.d):00007 * Edt/Rev YYYY/MM/DD Modified by ( turbos.d):00008 * Comment ( turbos.d):00009 * ---------------------------------------------------------------------------- ( turbos.d):00010 * 2023/08/11 Boisy Pitre ( turbos.d):00011 * Initial creation. ( turbos.d):00012 * ( turbos.d):00013 ******************************************************************************* ( turbos.d):00014 ( turbos.d):00015 ifne TURBOS.D-1 ( turbos.d):00016 0001 ( turbos.d):00017 TURBOS.D set 1 ( turbos.d):00018 ( turbos.d):00019 nam turbos.d ( turbos.d):00020 ttl TurbOS system definitions ( turbos.d):00021 ( turbos.d):00022 * Common definitions 0001 ( turbos.d):00023 true equ 1 0000 ( turbos.d):00024 false equ 0 ( turbos.d):00025 ( turbos.d):00026 pag ( turbos.d):00027 ***************************************** ( turbos.d):00028 * System service request code definitions ( turbos.d):00029 * ( turbos.d):00030 org 0 ( turbos.d):00031 * User and system state calls 0000 ( turbos.d):00032 F$Link rmb 1 link to module 0001 ( turbos.d):00033 F$Load rmb 1 load module from file 0002 ( turbos.d):00034 F$UnLink rmb 1 unlink module 0003 ( turbos.d):00035 F$Fork rmb 1 start new process 0004 ( turbos.d):00036 F$Wait rmb 1 wait for child process to die 0005 ( turbos.d):00037 F$Chain rmb 1 chain process to new module 0006 ( turbos.d):00038 F$Exit rmb 1 terminate process 0007 ( turbos.d):00039 F$Mem rmb 1 set memory size 0008 ( turbos.d):00040 F$Send rmb 1 send signal to process 0009 ( turbos.d):00041 F$Icpt rmb 1 set signal intercept 000A ( turbos.d):00042 F$Sleep rmb 1 suspend process 000B ( turbos.d):00043 F$ID rmb 1 return process ID 000C ( turbos.d):00044 F$SPrior rmb 1 set process priority 000D ( turbos.d):00045 F$SSWI rmb 1 set software interrupt 000E ( turbos.d):00046 F$PErr rmb 1 print Error 000F ( turbos.d):00047 F$PrsNam rmb 1 parse pathlist name 0010 ( turbos.d):00048 F$CmpNam rmb 1 compare two names 0011 ( turbos.d):00049 F$SchBit rmb 1 search bit map 0012 ( turbos.d):00050 F$AllBit rmb 1 allocate in bit map 0013 ( turbos.d):00051 F$DelBit rmb 1 deallocate in bit map 0014 ( turbos.d):00052 F$Time rmb 1 get current time 0015 ( turbos.d):00053 F$STime rmb 1 set current time 0016 ( turbos.d):00054 F$CRC rmb 1 generate CRC ( turbos.d):00055 ( turbos.d):00056 org $27 beginning of system reserved calls ( turbos.d):00057 * System state (privileged) calls 0027 ( turbos.d):00058 F$VIRQ rmb 1 install/delete virtual IRQ 0028 ( turbos.d):00059 F$SRqMem rmb 1 system memory request 0029 ( turbos.d):00060 F$SRtMem rmb 1 system memory return 002A ( turbos.d):00061 F$IRQ rmb 1 enter IRQ polling table 002B ( turbos.d):00062 F$IOQu rmb 1 enter I/O queue 002C ( turbos.d):00063 F$AProc rmb 1 enter active process queue 002D ( turbos.d):00064 F$NProc rmb 1 start next process 002E ( turbos.d):00065 F$VModul rmb 1 validate module 002F ( turbos.d):00066 F$Find64 rmb 1 find process/path descriptor 0030 ( turbos.d):00067 F$All64 rmb 1 allocate process/path descriptor 0031 ( turbos.d):00068 F$Ret64 rmb 1 return process/path descriptor 0032 ( turbos.d):00069 F$SSvc rmb 1 service request table initialization 0033 ( turbos.d):00070 F$IODel rmb 1 delete I/O module ( turbos.d):00071 ( turbos.d):00072 * ( turbos.d):00073 * System calls $70 through $7F are reserved for user definitions ( turbos.d):00074 * ( turbos.d):00075 org $70 0070 ( turbos.d):00076 rmb 16 reserved for user definition ( turbos.d):00077 ( turbos.d):00078 pag ( turbos.d):00079 ************************************** ( turbos.d):00080 * I/O service request code definitions ( turbos.d):00081 * ( turbos.d):00082 org $80 0080 ( turbos.d):00083 I$Attach rmb 1 attach I/O device 0081 ( turbos.d):00084 I$Detach rmb 1 detach I/O device 0082 ( turbos.d):00085 I$Dup rmb 1 duplicate path 0083 ( turbos.d):00086 I$Create rmb 1 create new file 0084 ( turbos.d):00087 I$Open rmb 1 open existing file 0085 ( turbos.d):00088 I$MakDir rmb 1 make directory file 0086 ( turbos.d):00089 I$ChgDir rmb 1 change default directory 0087 ( turbos.d):00090 I$Delete rmb 1 delete file 0088 ( turbos.d):00091 I$Seek rmb 1 change current position 0089 ( turbos.d):00092 I$Read rmb 1 read data 008A ( turbos.d):00093 I$Write rmb 1 write data 008B ( turbos.d):00094 I$ReadLn rmb 1 read line of ASCII data 008C ( turbos.d):00095 I$WritLn rmb 1 write line of ASCII data 008D ( turbos.d):00096 I$GetStt rmb 1 get path status 008E ( turbos.d):00097 I$SetStt rmb 1 set path status 008F ( turbos.d):00098 I$Close rmb 1 close path 0090 ( turbos.d):00099 I$DeletX rmb 1 delete from current exec dir ( turbos.d):00100 ( turbos.d):00101 ******************* ( turbos.d):00102 * File access modes ( turbos.d):00103 * 0001 ( turbos.d):00104 READ. equ %00000001 0002 ( turbos.d):00105 WRITE. equ %00000010 0003 ( turbos.d):00106 UPDAT. equ READ.+WRITE. 0004 ( turbos.d):00107 EXEC. equ %00000100 0008 ( turbos.d):00108 PREAD. equ %00001000 0010 ( turbos.d):00109 PWRIT. equ %00010000 0020 ( turbos.d):00110 PEXEC. equ %00100000 0040 ( turbos.d):00111 SHARE. equ %01000000 0080 ( turbos.d):00112 DIR. equ %10000000 0020 ( turbos.d):00113 ISIZ. equ %00100000 ( turbos.d):00114 ( turbos.d):00115 ************** ( turbos.d):00116 * Signal codes ( turbos.d):00117 * ( turbos.d):00118 org 0 0000 ( turbos.d):00119 S$Kill rmb 1 non-interceptable abort 0001 ( turbos.d):00120 S$Wake rmb 1 wake-up sleeping process 0002 ( turbos.d):00121 S$Abort rmb 1 keyboard abort 0003 ( turbos.d):00122 S$Intrpt rmb 1 keyboard interrupt ( turbos.d):00123 ( turbos.d):00124 pag ( turbos.d):00125 ********************************** ( turbos.d):00126 * Status codes for GetStat/SetStat ( turbos.d):00127 * ( turbos.d):00128 org 0 0000 ( turbos.d):00129 SS.Opt rmb 1 read/Write path descriptor options 0001 ( turbos.d):00130 SS.Ready rmb 1 check for device ready 0002 ( turbos.d):00131 SS.Size rmb 1 read/write file size 0003 ( turbos.d):00132 SS.Reset rmb 1 device restore 0004 ( turbos.d):00133 rmb 1 0005 ( turbos.d):00134 SS.Pos rmb 1 get file's current position 0006 ( turbos.d):00135 SS.EOF rmb 1 test for end of file 0007 ( turbos.d):00136 SS.Link rmb 1 link to status routines 0008 ( turbos.d):00137 SS.ULink rmb 1 unlink status routines 0009 ( turbos.d):00138 rmb 1 000A ( turbos.d):00139 SS.Frz rmb 1 freeze DD. information 000B ( turbos.d):00140 SS.SPT rmb 1 set DD.TKS to given value 000C ( turbos.d):00141 rmb 1 000D ( turbos.d):00142 SS.DCmd rmb 1 send direct command to disk 000E ( turbos.d):00143 SS.DevNm rmb 1 return device name (32-bytes at [X]) 000F ( turbos.d):00144 SS.FD rmb 1 return file descriptor (Y-bytes at [X]) 0010 ( turbos.d):00145 SS.Ticks rmb 1 set lockout honor duration 0011 ( turbos.d):00146 SS.Lock rmb 1 lock/release record 0012 ( turbos.d):00147 rmb 1 0013 ( turbos.d):00148 rmb 1 0014 ( turbos.d):00149 SS.BlkRd rmb 1 block read 0015 ( turbos.d):00150 SS.BlkWr rmb 1 block write 0016 ( turbos.d):00151 SS.Reten rmb 1 retension cycle 0017 ( turbos.d):00152 SS.WFM rmb 1 write file mark 0018 ( turbos.d):00153 SS.RFM rmb 1 read past file mark 0019 ( turbos.d):00154 SS.ELog rmb 1 read error log 001A ( turbos.d):00155 SS.SSig rmb 1 send signal on data ready 001B ( turbos.d):00156 SS.Relea rmb 1 release device 001C ( turbos.d):00157 rmb 1 001D ( turbos.d):00158 rmb 1 001E ( turbos.d):00159 SS.RsBit rmb 1 reserve bitmap sector (do not allocate in) LSB(X)=sct# 001F ( turbos.d):00160 rmb 1 reserved 0020 ( turbos.d):00161 rmb 1 0021 ( turbos.d):00162 rmb 3 0024 ( turbos.d):00163 rmb 1 0025 ( turbos.d):00164 rmb 1 0026 ( turbos.d):00165 rmb 1 0027 ( turbos.d):00166 rmb 1 0028 ( turbos.d):00167 SS.ComSt rmb 1 Getstat/SetStat for baud/parity 0029 ( turbos.d):00168 SS.Open rmb 1 SetStat to tell driver a path was opened 002A ( turbos.d):00169 SS.Close rmb 1 SetStat to tell driver a path was closed 002B ( turbos.d):00170 SS.HngUp rmb 1 SetStat to tell driver to hangup phone 002C ( turbos.d):00171 SS.FSig rmb 1 new signal for temp locked files 002D ( turbos.d):00172 rmb 19 ( turbos.d):00173 ( turbos.d):00174 org $A0 00A0 ( turbos.d):00175 rmb 1 00A1 ( turbos.d):00176 SS.Fill rmb 1 enable command-line history erase (scf) ( turbos.d):00177 ttl Direct Page Definitions ( turbos.d):00178 pag ( turbos.d):00179 ( turbos.d):00180 ********************************** ( turbos.d):00181 * Direct page variable definitions ( turbos.d):00182 * ( turbos.d):00183 org $00 ( turbos.d):00184 org $20 0020 ( turbos.d):00185 D.FMBM rmb 4 free memory bit map pointers 0024 ( turbos.d):00186 D.MLIM rmb 2 upper RAM memory limit 0026 ( turbos.d):00187 D.ModDir rmb 4 module directory pointers (start and end) 002A ( turbos.d):00188 D.Init rmb 2 configuration module base address 002C ( turbos.d):00189 D.SWI3 rmb 2 SWI3 vector 002E ( turbos.d):00190 D.SWI2 rmb 2 SWI2 vector 0030 ( turbos.d):00191 D.FIRQ rmb 2 FIRQ vector 0032 ( turbos.d):00192 D.IRQ rmb 2 IRQ vector 0034 ( turbos.d):00193 D.SWI rmb 2 SWI vector 0036 ( turbos.d):00194 D.NMI rmb 2 NMI vector 0038 ( turbos.d):00195 D.SvcIRQ rmb 2 interrupt service entry 003A ( turbos.d):00196 D.Poll rmb 2 interrupt polling routine 003C ( turbos.d):00197 D.UsrIRQ rmb 2 user interrupt routine 003E ( turbos.d):00198 D.SysIRQ rmb 2 system interrupt routine 0040 ( turbos.d):00199 D.UsrSvc rmb 2 user service request routine 0042 ( turbos.d):00200 D.SysSvc rmb 2 system service request routine 0044 ( turbos.d):00201 D.UsrDis rmb 2 user service request dispatch table 0046 ( turbos.d):00202 D.SysDis rmb 2 system service reuest dispatch table 0048 ( turbos.d):00203 D.Slice rmb 1 process time slice count 0049 ( turbos.d):00204 D.PrcDBT rmb 2 process descriptor block table 004B ( turbos.d):00205 D.Proc rmb 2 process descriptor address 004D ( turbos.d):00206 D.AProcQ rmb 2 active process queue 004F ( turbos.d):00207 D.WProcQ rmb 2 waiting process queue 0051 ( turbos.d):00208 D.SProcQ rmb 2 sleeping process queue 0053 ( turbos.d):00209 D.Time equ . time 0053 ( turbos.d):00210 D.Year rmb 1 current year 0054 ( turbos.d):00211 D.Month rmb 1 current month 0055 ( turbos.d):00212 D.Day rmb 1 current da 0056 ( turbos.d):00213 D.Hour rmb 1 current hour 0057 ( turbos.d):00214 D.Min rmb 1 current minute 0058 ( turbos.d):00215 D.Sec rmb 1 current second 0059 ( turbos.d):00216 D.Ticks rmb 4 number of ticks since boot 005D ( turbos.d):00217 D.Tick rmb 1 current tick 005E ( turbos.d):00218 D.TSec rmb 1 ticks per second 005F ( turbos.d):00219 D.TSlice rmb 1 ticks per time-slice 0060 ( turbos.d):00220 D.IOML rmb 2 I/O manager free memory low bound 0062 ( turbos.d):00221 D.IOMH rmb 2 I/O manager free memory hi bound 0064 ( turbos.d):00222 D.DevTbl rmb 2 device driver table address 0066 ( turbos.d):00223 D.PolTbl rmb 2 interrupt polling table address 0068 ( turbos.d):00224 D.PthDBT rmb 2 path descriptor block table addrress 006A ( turbos.d):00225 D.BTLO rmb 2 bootstrap low address 006C ( turbos.d):00226 D.BTHI rmb 2 bootstrap hi address 006E ( turbos.d):00227 D.Clock rmb 2 address of clock tick routine 0070 ( turbos.d):00228 D.Boot rmb 1 bootstrap attempted flag 0071 ( turbos.d):00229 D.URtoSs rmb 2 address of user to system routine (VIRQ) 0073 ( turbos.d):00230 D.VIRQTable rmb 2 pointer to virtual IRQ table 0075 ( turbos.d):00231 D.CRC rmb 1 CRC checking mode flag ( turbos.d):00232 ( turbos.d):00233 org $100 0100 ( turbos.d):00234 D.XSWI3 rmb 3 0103 ( turbos.d):00235 D.XSWI2 rmb 3 0106 ( turbos.d):00236 D.XSWI rmb 3 0109 ( turbos.d):00237 D.XNMI rmb 3 010C ( turbos.d):00238 D.XIRQ rmb 3 010F ( turbos.d):00239 D.XFIRQ rmb 3 ( turbos.d):00240 ( turbos.d):00241 * Table Sizes 0020 ( turbos.d):00242 BMAPSZ equ 65536/256/8 memory allocation bitmap table size 0002 ( turbos.d):00243 SVCTNM equ 2 number of service request tables 006E ( turbos.d):00244 SVCTSZ equ (256-BMAPSZ)/SVCTNM-2 service request table size ( turbos.d):00245 ( turbos.d):00246 ttl Structure Formats ( turbos.d):00247 pag ( turbos.d):00248 ************************************ ( turbos.d):00249 * Module directory entry definitions ( turbos.d):00250 * ( turbos.d):00251 org 0 0000 ( turbos.d):00252 MD$MPtr rmb 2 module pointer 0002 ( turbos.d):00253 MD$Link rmb 1 module link count 0003 ( turbos.d):00254 rmb 1 0004 ( turbos.d):00255 MD$ESize equ . module directory entry size ( turbos.d):00256 ( turbos.d):00257 ************************************ ( turbos.d):00258 * Module definitions ( turbos.d):00259 * ( turbos.d):00260 * Universal module offsets ( turbos.d):00261 * ( turbos.d):00262 org 0 0000 ( turbos.d):00263 M$ID rmb 2 ID code 0002 ( turbos.d):00264 M$Size rmb 2 module size 0004 ( turbos.d):00265 M$Name rmb 2 module name 0006 ( turbos.d):00266 M$Type rmb 1 type / language 0007 ( turbos.d):00267 M$Revs rmb 1 attributes / revision level 0008 ( turbos.d):00268 M$Parity rmb 1 header parity 0009 ( turbos.d):00269 M$IDSize equ . Mmdule ID size ( turbos.d):00270 ( turbos.d):00271 * ( turbos.d):00272 * Type-dependent module offsets ( turbos.d):00273 * ( turbos.d):00274 * System, file manager, device driver, program module ( turbos.d):00275 * 0009 ( turbos.d):00276 M$Exec rmb 2 execution entry offset ( turbos.d):00277 * ( turbos.d):00278 * Device driver, program module ( turbos.d):00279 * 000B ( turbos.d):00280 M$Mem rmb 2 stack requirement ( turbos.d):00281 * ( turbos.d):00282 * Device driver, device descriptor module ( turbos.d):00283 * 000D ( turbos.d):00284 M$Mode rmb 1 device driver mode capabilities ( turbos.d):00285 * ( turbos.d):00286 * Device descriptor module ( turbos.d):00287 * ( turbos.d):00288 org M$IDSize 0009 ( turbos.d):00289 M$FMgr rmb 2 file manager name offset 000B ( turbos.d):00290 M$PDev rmb 2 device driver name offset 000D ( turbos.d):00291 rmb 1 M$Mode (defined above) 000E ( turbos.d):00292 M$Port rmb 3 port address 0011 ( turbos.d):00293 M$Opt rmb 1 device default options 0012 ( turbos.d):00294 M$DTyp rmb 1 device type 0012 ( turbos.d):00295 IT.DTP equ M$DTyp descriptor type offset ( turbos.d):00296 ( turbos.d):00297 * ( turbos.d):00298 * Configuration module entry offsets ( turbos.d):00299 * ( turbos.d):00300 org M$IDSize 0009 ( turbos.d):00301 CM$MaxMem rmb 3 maximum free memory 000C ( turbos.d):00302 CM$PollCnt rmb 1 entries in interrupt polling table 000D ( turbos.d):00303 CM$DevCnt rmb 1 entries in device table 000E ( turbos.d):00304 CM$TickMod rmb 2 tick generator module name 0010 ( turbos.d):00305 CM$GoMod rmb 2 startup module name ( turbos.d):00306 ifne _FF_UNIFIED_IO 0012 ( turbos.d):00307 CM$StoreMod rmb 2 initial storage device name 0012 ( turbos.d):00308 CM$ConsoleMod rmb 2 initial console device name ( turbos.d):00309 endc ( turbos.d):00310 ifne _FF_BOOTING 0012 ( turbos.d):00311 CM$BootMod rmb 2 boot module name ( turbos.d):00312 endc 0014 ( turbos.d):00313 CM$OSLevel rmb 1 operating system level 0015 ( turbos.d):00314 CM$OSVer rmb 1 operating system version 0016 ( turbos.d):00315 CM$OSMajor rmb 1 operating system major 0017 ( turbos.d):00316 CM$OSMinor rmb 1 operating system minor 0018 ( turbos.d):00317 CM$Feature1 rmb 1 feature byte 1 0019 ( turbos.d):00318 CM$Feature2 rmb 1 feature byte 2 001A ( turbos.d):00319 rmb 4 reserved for future use ( turbos.d):00320 ( turbos.d):00321 * Feature1 byte definitions 0001 ( turbos.d):00322 CRCOn equ %00000001 CRC checking on 0000 ( turbos.d):00323 CRCOff equ %00000000 CRC checking off ( turbos.d):00324 ( turbos.d):00325 pag ( turbos.d):00326 ************************** ( turbos.d):00327 * Module field definitions ( turbos.d):00328 * ( turbos.d):00329 * ID field - first two bytes of a module ( turbos.d):00330 * 0087 ( turbos.d):00331 M$ID1 equ $87 module ID code byte one 00CD ( turbos.d):00332 M$ID2 equ $CD module ID code byte two 87CD ( turbos.d):00333 M$ID12 equ M$ID1*256+M$ID2 ( turbos.d):00334 ( turbos.d):00335 * ( turbos.d):00336 * Module type/language field masks ( turbos.d):00337 * 00F0 ( turbos.d):00338 TypeMask equ %11110000 type field 000F ( turbos.d):00339 LangMask equ %00001111 language field ( turbos.d):00340 ( turbos.d):00341 * ( turbos.d):00342 * Module type values ( turbos.d):00343 * 00F0 ( turbos.d):00344 Devic equ $F0 device descriptor module 00E0 ( turbos.d):00345 Drivr equ $E0 physical device driver 00D0 ( turbos.d):00346 FlMgr equ $D0 file manager 00C0 ( turbos.d):00347 Systm equ $C0 system module 0040 ( turbos.d):00348 Data equ $40 data module 0020 ( turbos.d):00349 Sbrtn equ $20 subroutine module 0010 ( turbos.d):00350 Prgrm equ $10 program module ( turbos.d):00351 ( turbos.d):00352 * ( turbos.d):00353 * Module language values ( turbos.d):00354 * 0001 ( turbos.d):00355 Objct equ 1 object code module ( turbos.d):00356 ( turbos.d):00357 * ( turbos.d):00358 * Module attributes / revision byte ( turbos.d):00359 * ( turbos.d):00360 * Field masks ( turbos.d):00361 * 00F0 ( turbos.d):00362 AttrMask equ %11110000 attributes field 000F ( turbos.d):00363 RevsMask equ %00001111 revision level field ( turbos.d):00364 ( turbos.d):00365 * ( turbos.d):00366 * Attribute flags ( turbos.d):00367 * 0080 ( turbos.d):00368 ReEnt equ %10000000 re-entrant module ( turbos.d):00369 ( turbos.d):00370 ******************** ( turbos.d):00371 * Device type values ( turbos.d):00372 * ( turbos.d):00373 * These values define various classes of devices, which are ( turbos.d):00374 * managed by a file manager module. The device type is embedded ( turbos.d):00375 * in a device descriptor. ( turbos.d):00376 * 0000 ( turbos.d):00377 DT.SCF equ 0 sequential character file manager 0001 ( turbos.d):00378 DT.RBF equ 1 random block file manager 0002 ( turbos.d):00379 DT.Pipe equ 2 pipe file manager ( turbos.d):00380 ( turbos.d):00381 ********************* ( turbos.d):00382 * CRC result constant ( turbos.d):00383 * 0080 ( turbos.d):00384 CRCCon1 equ $80 0FE3 ( turbos.d):00385 CRCCon23 equ $0FE3 ( turbos.d):00386 ( turbos.d):00387 ttl Process Information ( turbos.d):00388 pag ( turbos.d):00389 ******************************** ( turbos.d):00390 * Process descriptor definitions ( turbos.d):00391 * 000C ( turbos.d):00392 DefIOSiz equ 12 0010 ( turbos.d):00393 NumPaths equ 16 number of local paths ( turbos.d):00394 ( turbos.d):00395 org 0 0000 ( turbos.d):00396 P$ID rmb 1 process ID 0001 ( turbos.d):00397 P$PID rmb 1 parent's ID 0002 ( turbos.d):00398 P$SID rmb 1 sibling's ID 0003 ( turbos.d):00399 P$CID rmb 1 child's ID 0004 ( turbos.d):00400 P$SP rmb 2 stack pointer 0006 ( turbos.d):00401 P$CHAP rmb 1 process chapter number 0007 ( turbos.d):00402 P$ADDR rmb 1 user address beginning page number 0008 ( turbos.d):00403 P$PagCnt rmb 1 memory page count 0009 ( turbos.d):00404 P$User rmb 2 user index 000B ( turbos.d):00405 P$Prior rmb 1 priority 000C ( turbos.d):00406 P$Age rmb 1 age 000D ( turbos.d):00407 P$State rmb 1 status 000E ( turbos.d):00408 P$Queue rmb 2 queue link (process pointer) 0010 ( turbos.d):00409 P$IOQP rmb 1 previous I/O queue link (process ID) 0011 ( turbos.d):00410 P$IOQN rmb 1 next I/O queue link (process ID) 0012 ( turbos.d):00411 P$PModul rmb 2 primary module 0014 ( turbos.d):00412 P$SWI rmb 2 SWI entry point 0016 ( turbos.d):00413 P$SWI2 rmb 2 SWI2 entry point 0018 ( turbos.d):00414 P$SWI3 rmb 2 SWI3 entry point 001A ( turbos.d):00415 P$DIO rmb DefIOSiz default I/O pointers 0026 ( turbos.d):00416 P$PATH rmb NumPaths I/O path table 0036 ( turbos.d):00417 P$Signal rmb 1 signal code 0037 ( turbos.d):00418 P$SigVec rmb 2 signal intercept vector 0039 ( turbos.d):00419 P$SigDat rmb 2 signal intercept data address 003B ( turbos.d):00420 P$NIO rmb 4 003F ( turbos.d):00421 rmb $40-. unused 0040 ( turbos.d):00422 P$Size equ . size of process descriptor ( turbos.d):00423 ( turbos.d):00424 * ( turbos.d):00425 * Process state flags ( turbos.d):00426 * 0080 ( turbos.d):00427 SysState equ %10000000 0040 ( turbos.d):00428 TimSleep equ %01000000 0020 ( turbos.d):00429 TimOut equ %00100000 0010 ( turbos.d):00430 ImgChg equ %00010000 0002 ( turbos.d):00431 Condem equ %00000010 0001 ( turbos.d):00432 Dead equ %00000001 ( turbos.d):00433 ( turbos.d):00434 ttl I/O Definitions ( turbos.d):00435 pag ( turbos.d):00436 ************************* ( turbos.d):00437 * Path descriptor offsets ( turbos.d):00438 * ( turbos.d):00439 org 0 0000 ( turbos.d):00440 PD.PD rmb 1 path number 0001 ( turbos.d):00441 PD.MOD rmb 1 mode (read/write/update) 0002 ( turbos.d):00442 PD.CNT rmb 1 number of open images 0003 ( turbos.d):00443 PD.DEV rmb 2 device table entry address 0005 ( turbos.d):00444 PD.CPR rmb 1 current process 0006 ( turbos.d):00445 PD.RGS rmb 2 caller's register stack 0008 ( turbos.d):00446 PD.BUF rmb 2 buffer address 000A ( turbos.d):00447 PD.FST rmb 32-. file manager's storage 0020 ( turbos.d):00448 PD.OPT equ . path descriptor options 0020 ( turbos.d):00449 PD.DTP rmb 1 device type 0021 ( turbos.d):00450 rmb 64-. path options end 0040 ( turbos.d):00451 PDSIZE equ . ( turbos.d):00452 ( turbos.d):00453 * ( turbos.d):00454 * Pathlist special symbols ( turbos.d):00455 * 002F ( turbos.d):00456 PDELIM equ '/ pathlist name separator 002E ( turbos.d):00457 PDIR equ '. directory 0040 ( turbos.d):00458 PENTIR equ '@ entire device ( turbos.d):00459 ( turbos.d):00460 pag ( turbos.d):00461 **************************** ( turbos.d):00462 * File manager entry offsets ( turbos.d):00463 * ( turbos.d):00464 org 0 0000 ( turbos.d):00465 FMCREA rmb 3 create (open new) file 0003 ( turbos.d):00466 FMOPEN rmb 3 open file 0006 ( turbos.d):00467 FMMDIR rmb 3 make directory 0009 ( turbos.d):00468 FMCDIR rmb 3 change directory 000C ( turbos.d):00469 FMDLET rmb 3 delete file 000F ( turbos.d):00470 FMSEEK rmb 3 position file 0012 ( turbos.d):00471 FMREAD rmb 3 read from file 0015 ( turbos.d):00472 FMWRIT rmb 3 write to file 0018 ( turbos.d):00473 FMRDLN rmb 3 read line 001B ( turbos.d):00474 FMWRLN rmb 3 write line 001E ( turbos.d):00475 FMGSTA rmb 3 get file status 0021 ( turbos.d):00476 FMSSTA rmb 3 set file status 0024 ( turbos.d):00477 FMCLOS rmb 3 close file ( turbos.d):00478 ( turbos.d):00479 ***************************** ( turbos.d):00480 * Device driver entry offsets ( turbos.d):00481 * ( turbos.d):00482 org 0 0000 ( turbos.d):00483 D$INIT rmb 3 device initialization 0003 ( turbos.d):00484 D$READ rmb 3 read from device 0006 ( turbos.d):00485 D$WRIT rmb 3 write to device 0009 ( turbos.d):00486 D$GSTA rmb 3 get device status 000C ( turbos.d):00487 D$PSTA rmb 3 put device status 000F ( turbos.d):00488 D$TERM rmb 3 device termination ( turbos.d):00489 ( turbos.d):00490 ********************* ( turbos.d):00491 * Device table format ( turbos.d):00492 * ( turbos.d):00493 org 0 0000 ( turbos.d):00494 V$DRIV rmb 2 device driver module 0002 ( turbos.d):00495 V$STAT rmb 2 device driver static storage 0004 ( turbos.d):00496 V$DESC rmb 2 device descriptor module 0006 ( turbos.d):00497 V$FMGR rmb 2 file manager module 0008 ( turbos.d):00498 V$USRS rmb 1 use count 0009 ( turbos.d):00499 DEVSIZ equ . ( turbos.d):00500 ( turbos.d):00501 ******************************* ( turbos.d):00502 * Device static storage offsets ( turbos.d):00503 * ( turbos.d):00504 org 0 0000 ( turbos.d):00505 V.PAGE rmb 1 port extended address 0001 ( turbos.d):00506 V.PORT rmb 2 device 'base' port address 0003 ( turbos.d):00507 V.LPRC rmb 1 last active process ID 0004 ( turbos.d):00508 V.BUSY rmb 1 active process ID (0=not busy) 0005 ( turbos.d):00509 V.WAKE rmb 1 active process descriptor if driver MUST wake-up 0006 ( turbos.d):00510 V.USER equ . driver allocation origin ( turbos.d):00511 ( turbos.d):00512 ******************************** ( turbos.d):00513 * Interrupt polling table format ( turbos.d):00514 * ( turbos.d):00515 org 0 0000 ( turbos.d):00516 Q$Poll rmb 2 absolute polling address 0002 ( turbos.d):00517 Q$Flip rmb 1 flip (EOR) byte; normally zero 0003 ( turbos.d):00518 Q$Mask rmb 1 polling mask (after flip) 0004 ( turbos.d):00519 Q$Serv rmb 2 absolute service routine Address 0006 ( turbos.d):00520 Q$Stat rmb 2 static storage address 0008 ( turbos.d):00521 Q$Prty rmb 1 priority (low numbers=top priority) 0009 ( turbos.d):00522 POLSIZ equ . ( turbos.d):00523 ( turbos.d):00524 ******************** ( turbos.d):00525 * VIRQ packet format ( turbos.d):00526 * ( turbos.d):00527 org 0 0000 ( turbos.d):00528 Vi.Cnt rmb 2 count down counter 0002 ( turbos.d):00529 Vi.Rst rmb 2 reset value for counter 0004 ( turbos.d):00530 Vi.Stat rmb 1 status byte 0005 ( turbos.d):00531 Vi.PkSz equ . ( turbos.d):00532 0001 ( turbos.d):00533 Vi.IFlag equ %00000001 status byte virq flag ( turbos.d):00534 ( turbos.d):00535 pag ( turbos.d):00536 ************************************* ( turbos.d):00537 * Machine characteristics definitions ( turbos.d):00538 * 0000 ( turbos.d):00539 R$CC equ 0 condition codes register 0001 ( turbos.d):00540 R$A equ 1 A accumulator 0002 ( turbos.d):00541 R$B equ 2 B accumulator 0001 ( turbos.d):00542 R$D equ R$A combined A:B accumulator 0003 ( turbos.d):00543 R$DP equ 3 direct page register 0004 ( turbos.d):00544 R$X equ 4 X index register 0006 ( turbos.d):00545 R$Y equ 6 Y index register 0008 ( turbos.d):00546 R$U equ 8 user stack register 000A ( turbos.d):00547 R$PC equ 10 program counter register 000C ( turbos.d):00548 R$Size equ 12 total register package size ( turbos.d):00549 0080 ( turbos.d):00550 Entire equ %10000000 full register stack flag 0040 ( turbos.d):00551 FIRQMask equ %01000000 fast interrupt mask bit 0020 ( turbos.d):00552 HalfCrry equ %00100000 half carry flag 0010 ( turbos.d):00553 IRQMask equ %00010000 interrupt mask bit 0008 ( turbos.d):00554 Negative equ %00001000 negative flag 0004 ( turbos.d):00555 Zero equ %00000100 zero flag 0002 ( turbos.d):00556 TwosOvfl equ %00000010 two's complement overflow flag 0001 ( turbos.d):00557 Carry equ %00000001 carry bit 0050 ( turbos.d):00558 IntMasks equ IRQMask+FIRQMask 0080 ( turbos.d):00559 Sign equ %10000000 sign bit ( turbos.d):00560 ( turbos.d):00561 ttl Error code definitions ( turbos.d):00562 pag ( turbos.d):00563 ************************ ( turbos.d):00564 * Error code definitions ( turbos.d):00565 * ( turbos.d):00566 org 200 00C8 ( turbos.d):00567 E$PthFul rmb 1 path table full 00C9 ( turbos.d):00568 E$BPNum rmb 1 bad path number 00CA ( turbos.d):00569 E$Poll rmb 1 polling table Full 00CB ( turbos.d):00570 E$BMode rmb 1 bad Mode 00CC ( turbos.d):00571 E$DevOvf rmb 1 device table overflow 00CD ( turbos.d):00572 E$BMID rmb 1 bad module ID 00CE ( turbos.d):00573 E$DirFul rmb 1 module directory full 00CF ( turbos.d):00574 E$MemFul rmb 1 process memory full 00D0 ( turbos.d):00575 E$UnkSvc rmb 1 unknown service code 00D1 ( turbos.d):00576 E$ModBsy rmb 1 module busy 00D2 ( turbos.d):00577 E$BPAddr rmb 1 bad page address 00D3 ( turbos.d):00578 E$EOF rmb 1 end of file 00D4 ( turbos.d):00579 rmb 1 00D5 ( turbos.d):00580 E$NES rmb 1 non-existent segment 00D6 ( turbos.d):00581 E$FNA rmb 1 file not accesible 00D7 ( turbos.d):00582 E$BPNam rmb 1 bad path name 00D8 ( turbos.d):00583 E$PNNF rmb 1 path name Not Found 00D9 ( turbos.d):00584 E$SLF rmb 1 segment list full 00DA ( turbos.d):00585 E$CEF rmb 1 creating existing file 00DB ( turbos.d):00586 E$IBA rmb 1 illegal block address 00DC ( turbos.d):00587 E$HangUp rmb 1 carrier detect lost 00DD ( turbos.d):00588 E$MNF rmb 1 module not found 00DE ( turbos.d):00589 rmb 1 00DF ( turbos.d):00590 E$DelSP rmb 1 deleting stack pointer memory 00E0 ( turbos.d):00591 E$IPrcID rmb 1 illegal process ID 00E0 ( turbos.d):00592 E$BPrcID equ E$IPrcID bad process ID 00E1 ( turbos.d):00593 rmb 1 00E2 ( turbos.d):00594 E$NoChld rmb 1 no children 00E3 ( turbos.d):00595 E$ISWI rmb 1 illegal SWI code 00E4 ( turbos.d):00596 E$PrcAbt rmb 1 process aborted 00E5 ( turbos.d):00597 E$PrcFul rmb 1 process table full 00E6 ( turbos.d):00598 E$IForkP rmb 1 illegal fork parameter 00E7 ( turbos.d):00599 E$KwnMod rmb 1 known module 00E8 ( turbos.d):00600 E$BMCRC rmb 1 bad module CRC 00E9 ( turbos.d):00601 E$USigP rmb 1 unprocessed signal pending 00EA ( turbos.d):00602 E$NEMod rmb 1 non-existent module 00EB ( turbos.d):00603 E$BNam rmb 1 bad name 00EC ( turbos.d):00604 E$BMHP rmb 1 bad module header parity 00ED ( turbos.d):00605 E$NoRAM rmb 1 no system RAM available 00EE ( turbos.d):00606 E$DNE rmb 1 directory not empty 00EF ( turbos.d):00607 E$NoTask rmb 1 no available task number ( turbos.d):00608 rmb $F0-. reserved 00F0 ( turbos.d):00609 E$Unit rmb 1 illegal media unit 00F1 ( turbos.d):00610 E$Sect rmb 1 bad sector number 00F2 ( turbos.d):00611 E$WP rmb 1 write protect 00F3 ( turbos.d):00612 E$CRC rmb 1 bad checksum 00F4 ( turbos.d):00613 E$Read rmb 1 read error 00F5 ( turbos.d):00614 E$Write rmb 1 write error 00F6 ( turbos.d):00615 E$NotRdy rmb 1 device not ready 00F7 ( turbos.d):00616 E$Seek rmb 1 seek error 00F8 ( turbos.d):00617 E$Full rmb 1 media full 00F9 ( turbos.d):00618 E$BTyp rmb 1 bad type (incompatible) media 00FA ( turbos.d):00619 E$DevBsy rmb 1 device busy 00FB ( turbos.d):00620 E$DIDC rmb 1 media ID change 00FC ( turbos.d):00621 E$Lock rmb 1 record is busy (locked out) 00FD ( turbos.d):00622 E$Share rmb 1 non-sharable file busy 00FE ( turbos.d):00623 E$DeadLk rmb 1 I/O deadlock error ( turbos.d):00624 ( turbos.d):00625 * Character definitions 0020 ( turbos.d):00626 C$Space set $20 002E ( turbos.d):00627 C$Period set '. 002C ( turbos.d):00628 C$Comma set ', 000D ( turbos.d):00629 C$CR set $0D 000A ( turbos.d):00630 C$LF set $0A ( turbos.d):00631 ( turbos.d):00632 endc ( defs.d):00025 ( defs.d):00026 * F256 Jr. specific definitions ( defs.d):00027 use f256.d ( f256.d):00001 ifne F256.D-1 0001 ( f256.d):00002 F256.D set 1 ( f256.d):00003 ( f256.d):00004 ******************************************************************** ( f256.d):00005 * F256Defs - NitrOS-9 System Definitions for the Foenix F256 ( f256.d):00006 * ( f256.d):00007 * This is a high level view of the F256 memory map as setup by ( f256.d):00008 * NitrOS-9. ( f256.d):00009 * ( f256.d):00010 * $0000----> ================================== ( f256.d):00011 * | | ( f256.d):00012 * | NitrOS-9 Globals/Stack | ( f256.d):00013 * | | ( f256.d):00014 * $0500---->|==================================| ( f256.d):00015 * | | ( f256.d):00016 * . . . . . . . . . . . . . . . . . ( f256.d):00017 * | | ( f256.d):00018 * | RAM available for allocation | ( f256.d):00019 * | by NitrOS-9 and Apps | ( f256.d):00020 * | | ( f256.d):00021 * . . . . . . . . . . . . . . . . . ( f256.d):00022 * | | ( f256.d):00023 * $FD00---->|==================================| ( f256.d):00024 * | Constant RAM (for Level 2) | ( f256.d):00025 * $FE00---->|==================================| ( f256.d):00026 * | I/O | ( f256.d):00027 * | & Vectors | ( f256.d):00028 * ================================== ( f256.d):00029 * ( f256.d):00030 * F256 hardware is documented here: ( f256.d):00031 * https://github.com/pweingar/C256jrManual/blob/main/tex/f256jr_ref.pdf ( f256.d):00032 * ( f256.d):00033 * $Id$ ( f256.d):00034 * ( f256.d):00035 * Edt/Rev YYYY/MM/DD Modified by ( f256.d):00036 * Comment ( f256.d):00037 * ------------------------------------------------------------------ ( f256.d):00038 * 2023/02/07 Boisy G. Pitre ( f256.d):00039 * Started. ( f256.d):00040 * ( f256.d):00041 * 2023/08/16 Boisy G. Pitre ( f256.d):00042 * Modified to address new memory map that Stefany created. ( f256.d):00043 ( f256.d):00044 ******************************************************************** ( f256.d):00045 * Ticks per second ( f256.d):00046 * 003C ( f256.d):00047 TkPerSec set 60 ( f256.d):00048 ( f256.d):00049 ifeq Level-1 ( f256.d):00050 ( f256.d):00051 ******************************************************************** ( f256.d):00052 * ( f256.d):00053 * NitrOS-9 Level 1 Section ( f256.d):00054 * ( f256.d):00055 ******************************************************************** ( f256.d):00056 ( f256.d):00057 ******************************************************************** ( f256.d):00058 * Boot definitions for NitrOS-9 Level 1 ( f256.d):00059 * ( f256.d):00060 * These definitions are not strictly for 'Boot', but are for booting the ( f256.d):00061 * system. ( f256.d):00062 * 00FF ( f256.d):00063 HW.Page set $FF device descriptor hardware page ( f256.d):00064 ( f256.d):00065 else ( f256.d):00066 0007 ( f256.d):00067 HW.Page set $07 device descriptor hardware page EE00 ( f256.d):00068 Bt.Start set $EE00 start address of where KRN is in memory ( f256.d):00069 ( f256.d):00070 ************************************************* ( f256.d):00071 * ( f256.d):00072 * NitrOS-9 Level 2 Section ( f256.d):00073 * ( f256.d):00074 ************************************************* ( f256.d):00075 ( f256.d):00076 **************************************** ( f256.d):00077 * Dynamic Address Translator Definitions ( f256.d):00078 * 0008 ( f256.d):00079 DAT.BlCt EQU 8 DAT blocks/address space 2000 ( f256.d):00080 DAT.BlSz EQU (256/DAT.BlCt)*256 DAT block size 0010 ( f256.d):00081 DAT.ImSz EQU DAT.BlCt*2 DAT image size FFE0 ( f256.d):00082 DAT.Addr EQU -(DAT.BlSz/256) DAT MSB address bits FFA0 ( f256.d):00083 DAT.Task EQU $FFA0 task register address 0020 ( f256.d):00084 DAT.TkCt EQU 32 number of DAT tasks FFA8 ( f256.d):00085 DAT.Regs EQU $FFA8 DAT block registers base address 333E ( f256.d):00086 DAT.Free EQU $333E free block number 003F ( f256.d):00087 DAT.BlMx EQU $3F maximum block number 0040 ( f256.d):00088 DAT.BMSz EQU $40 memory block map size 0000 ( f256.d):00089 DAT.WrPr EQU 0 no write protect 0000 ( f256.d):00090 DAT.WrEn EQU 0 no write enable 0000 ( f256.d):00091 SysTask EQU 0 CoCo system task number 003F ( f256.d):00092 IOBlock EQU $3F 003F ( f256.d):00093 ROMBlock EQU $3F 007F ( f256.d):00094 IOAddr EQU $7F 0001 ( f256.d):00095 ROMCount EQU 1 number of blocks of ROM (high RAM block) 0001 ( f256.d):00096 RAMCount EQU 1 initial blocks of RAM 0005 ( f256.d):00097 MoveBlks EQU DAT.BlCt-ROMCount-2 block numbers used for copies 0001 ( f256.d):00098 BlockTyp EQU 1 check only first bytes of RAM block 0002 ( f256.d):00099 ByteType EQU 2 check entire block of RAM 0001 ( f256.d):00100 Limited EQU 1 check only upper memory for ROM modules 0002 ( f256.d):00101 UnLimitd EQU 2 check all NotRAM for modules ( f256.d):00102 * NOTE: this check assumes any NotRAM with a module will ( f256.d):00103 * always start with $87CD in first two bytes of block 0001 ( f256.d):00104 RAMCheck EQU BlockTyp check only beg bytes of block 0001 ( f256.d):00105 ROMCheck EQU Limited check only upper few blocks for ROM 003F ( f256.d):00106 LastRAM EQU IOBlock maximum RAM block number ( f256.d):00107 0007 ( f256.d):00108 HW.Page SET $7 device descriptor hardware page ( f256.d):00109 ( f256.d):00110 * KrnBlk defines the block number of the 8K RAM block that is mapped to ( f256.d):00111 * the top of CPU address space ($E000-$FFFF) for the system process, and ( f256.d):00112 * which holds the Kernel. The top 3 pages of this CPU address space ($FD00- ( f256.d):00113 * $FFFF) have two special properties. First, $FE00-$FFFF contains the I/O space. ( f256.d):00114 * Second, $FD00-$FDFFF isn't affected by the DAT mappings but, instead, ( f256.d):00115 * remains constant regardless of what block is mapped in at slot 7. ( f256.d):00116 * When a user process is mapped in, and requests enough memory, it will end up ( f256.d):00117 * with its own block assigned for CPU address space $E000- ( f256.d):00118 * $FFFF but $FD00-$FFFF is unusable by the user process. 0007 ( f256.d):00119 KrnBlk SET $7 ( f256.d):00120 ( f256.d):00121 endc ( f256.d):00122 ( f256.d):00123 ******************************************************************** ( f256.d):00124 * System control definitions ( f256.d):00125 * FE00 ( f256.d):00126 SYS0 equ $FE00 FE01 ( f256.d):00127 SYS1 equ $FE01 FE02 ( f256.d):00128 RST0 equ $FE02 FE03 ( f256.d):00129 RST1 equ $FE03 ( f256.d):00130 0080 ( f256.d):00131 SYS_RESET equ %10000000 0020 ( f256.d):00132 SYS_CAP_EN equ %00100000 0010 ( f256.d):00133 SYS_BUZZ equ %00010000 0008 ( f256.d):00134 SYS_L1 equ %00001000 0004 ( f256.d):00135 SYS_L0 equ %00000100 0002 ( f256.d):00136 SYS_SD_L equ %00000010 0001 ( f256.d):00137 SYS_PWR_L equ %00000001 ( f256.d):00138 0080 ( f256.d):00139 SYS_SD_WP equ %10000000 0040 ( f256.d):00140 SYS_SD_CD equ %01000000 00C0 ( f256.d):00141 SYS_L1_RATE equ %11000000 0030 ( f256.d):00142 SYS_L0_RATE equ %00110000 0008 ( f256.d):00143 SYS_SID_ST equ %00001000 0004 ( f256.d):00144 SYS_PSG_ST equ %00000100 0002 ( f256.d):00145 SYS_L1_MN equ %00000010 0001 ( f256.d):00146 SYS_L0_MN equ %00000001 ( f256.d):00147 ( f256.d):00148 ******************************************************************** ( f256.d):00149 * F256 MMU definitions ( f256.d):00150 * FFA0 ( f256.d):00151 MMU_MEM_CTRL equ $FFA0 FFA1 ( f256.d):00152 MMU_IO_CTRL equ $FFA1 FFA8 ( f256.d):00153 MMU_SLOT_0 equ $FFA8 $0000-$1FFF FFA9 ( f256.d):00154 MMU_SLOT_1 equ $FFA9 $2000-$3FFF FFAA ( f256.d):00155 MMU_SLOT_2 equ $FFAA $4000-$5FFF FFAB ( f256.d):00156 MMU_SLOT_3 equ $FFAB $6000-$7FFF FFAC ( f256.d):00157 MMU_SLOT_4 equ $FFAC $8000-$9FFF FFAD ( f256.d):00158 MMU_SLOT_5 equ $FFAD $A000-$BFFF FFAE ( f256.d):00159 MMU_SLOT_6 equ $FFAE $C000-$DFFF FFAF ( f256.d):00160 MMU_SLOT_7 equ $FFAF $E000-$FFFF ( f256.d):00161 ( f256.d):00162 * MMU_MEM_CTRL bits 0030 ( f256.d):00163 EDIT_LUT equ %00110000 0000 ( f256.d):00164 EDIT_LUT_0 equ %00000000 0010 ( f256.d):00165 EDIT_LUT_1 equ %00010000 0020 ( f256.d):00166 EDIT_LUT_2 equ %00100000 0030 ( f256.d):00167 EDIT_LUT_3 equ %00110000 0000 ( f256.d):00168 ACT_LUT equ %00000000 0000 ( f256.d):00169 ACT_LUT_0 equ %00000000 0001 ( f256.d):00170 ACT_LUT_1 equ %00000001 0002 ( f256.d):00171 ACT_LUT_2 equ %00000010 0003 ( f256.d):00172 ACT_LUT_3 equ %00000011 ( f256.d):00173 0008 ( f256.d):00174 LUT_BANK_0 equ $0008 0009 ( f256.d):00175 LUT_BANK_1 equ $0009 000A ( f256.d):00176 LUT_BANK_2 equ $000A 000B ( f256.d):00177 LUT_BANK_3 equ $000B 000C ( f256.d):00178 LUT_BANK_4 equ $000C 000D ( f256.d):00179 LUT_BANK_5 equ $000D 000E ( f256.d):00180 LUT_BANK_6 equ $000E 000F ( f256.d):00181 LUT_BANK_7 equ $000F ( f256.d):00182 ( f256.d):00183 * MMU_IO_CTRL bits ( f256.d):00184 * $FFA1 has 2 bits: ( f256.d):00185 * FFA1[0] = ( f256.d):00186 * 1 = Enable internal RAM for segment $FD00-$FDFF. ( f256.d):00187 * 0 = Disable; RAM/FLASH is accessible. ( f256.d):00188 * ( f256.d):00189 * FFA1[1] = ( f256.d):00190 * 1 = Enable internal RAM for segment $FFF0-$FFFF ( f256.d):00191 * 0 = Disable; RAM/FLASH is accessible. ( f256.d):00192 * When enabled, the areas supersede RAM/flash, but will be disabled by RESET. When the system resets, ( f256.d):00193 * those regions revert to RAM/flash. Also at RESET, the contents of RAM retain the old values until the ( f256.d):00194 * system powers off. ( f256.d):00195 ( f256.d):00196 ******************************************************************** ( f256.d):00197 * F256 interrupt definitions ( f256.d):00198 * ( f256.d):00199 * Interrupt addresses FE20 ( f256.d):00200 INT_PENDING_0 equ $FE20 FE24 ( f256.d):00201 INT_POLARITY_0 equ $FE24 FE28 ( f256.d):00202 INT_EDGE_0 equ $FE28 FE2C ( f256.d):00203 INT_MASK_0 equ $FE2C ( f256.d):00204 FE21 ( f256.d):00205 INT_PENDING_1 equ $FE21 FE25 ( f256.d):00206 INT_POLARITY_1 equ $FE25 FE29 ( f256.d):00207 INT_EDGE_1 equ $FE29 FE2D ( f256.d):00208 INT_MASK_1 equ $FE2D ( f256.d):00209 FE22 ( f256.d):00210 INT_PENDING_2 equ $FE22 not used FE26 ( f256.d):00211 INT_POLARITY_2 equ $FE26 not used FE2A ( f256.d):00212 INT_EDGE_2 equ $FE2A not used FE2E ( f256.d):00213 INT_MASK_2 equ $FE2E not used ( f256.d):00214 FE23 ( f256.d):00215 INT_PENDING_3 equ $FE23 not used FE27 ( f256.d):00216 INT_POLARITY_3 equ $FE27 not used FE2B ( f256.d):00217 INT_EDGE_3 equ $FE2B not used FE2F ( f256.d):00218 INT_MASK_3 equ $FE2F not used ( f256.d):00219 ( f256.d):00220 * Interrupt Group 0 Flags 0001 ( f256.d):00221 INT_VKY_SOF equ %00000001 TinyVicky start of frame interrupt 0002 ( f256.d):00222 INT_VKY_SOL equ %00000010 TinyVicky start of line interrupt 0004 ( f256.d):00223 INT_PS2_KBD equ %00000100 PS/2 keyboard event 0008 ( f256.d):00224 INT_PS2_MOUSE equ %00001000 PS/2 mouse event 0010 ( f256.d):00225 INT_TIMER_0 equ %00010000 TIMER0 has reached its target value 0010 ( f256.d):00226 INT_TIMER_1 equ %00010000 TIMER1 has reached its target value 0080 ( f256.d):00227 INT_CARTRIDGE equ %10000000 Interrupt asserted by the cartridge ( f256.d):00228 ( f256.d):00229 * Interrupt Group 1 Flags 0001 ( f256.d):00230 INT_UART equ %00000001 UART is ready to receive or send data 0010 ( f256.d):00231 INT_RTC equ %00010000 event from the real time clock chip 0020 ( f256.d):00232 INT_VIA0 equ %00100000 event from the 65C22 VIA chip 0040 ( f256.d):00233 INT_VIA1 equ %01000000 F256K Only: local keyboard 0040 ( f256.d):00234 INT_SDC_INS equ %01000000 yser has inserted an SD card ( f256.d):00235 ( f256.d):00236 * Interrupt Group 2 Flags 0001 ( f256.d):00237 IEC_DATA_i equ %00000001 IEC data in 0002 ( f256.d):00238 IEC_CLK_i equ %00000010 IEC clock in 0004 ( f256.d):00239 IEC_ATN_i equ %00000100 IEC ATN in 0008 ( f256.d):00240 IEC_SREQ_i equ %00001000 IEC SREQ in ( f256.d):00241 ( f256.d):00242 ******************************************************************** ( f256.d):00243 * F256 keyboard definitions ( f256.d):00244 * FE50 ( f256.d):00245 PS2_CTRL equ $FE50 FE51 ( f256.d):00246 PS2_OUT equ $FE51 FE52 ( f256.d):00247 KBD_IN equ $FE52 FE53 ( f256.d):00248 MS_IN equ $FE53 FE54 ( f256.d):00249 PS2_STAT equ $FE54 ( f256.d):00250 0020 ( f256.d):00251 MCLR equ %00100000 0010 ( f256.d):00252 KCLR equ %00010000 0008 ( f256.d):00253 M_WR equ %00001000 0002 ( f256.d):00254 K_WR equ %00000010 ( f256.d):00255 0080 ( f256.d):00256 K_AK equ %10000000 0040 ( f256.d):00257 K_NK equ %01000000 0020 ( f256.d):00258 M_AK equ %00100000 0010 ( f256.d):00259 M_NK equ %00010000 0002 ( f256.d):00260 MEMP equ %00000010 0001 ( f256.d):00261 KEMP equ %00000001 ( f256.d):00262 ( f256.d):00263 ******************************************************************** ( f256.d):00264 * F256 timer definitions ( f256.d):00265 * ( f256.d):00266 * Timer addresses FE30 ( f256.d):00267 T0_CTR equ $FE30 timer 0 counter (write) FE30 ( f256.d):00268 T0_STAT equ $FE30 timer 0 status (read) FE31 ( f256.d):00269 T0_VAL equ $FE31 timer 0 value (read/write) FE34 ( f256.d):00270 T0_CMP_CTR equ $FE34 timer 0 compare counter (read/write) FE35 ( f256.d):00271 T0_CMP equ $FE35 timer 0 compare value (read/write) FE38 ( f256.d):00272 T1_CTR equ $FE38 timer 1 counter (write) FE38 ( f256.d):00273 T1_STAT equ $FE38 timer 1 status (read) FE39 ( f256.d):00274 T1_VAL equ $FE39 timer 1 value (read/write) FE3C ( f256.d):00275 T1_CMP_CTR equ $FE3C timer 1 compare counter (read/write) FE3D ( f256.d):00276 T1_CMP equ $FE3D timer 1 compare value (read/write) ( f256.d):00277 ( f256.d):00278 ******************************************************************** ( f256.d):00279 * F256 VIA definitions ( f256.d):00280 * ( f256.d):00281 * VIA addresses FFB0 ( f256.d):00282 IORB equ $FFB0 port b data FFB1 ( f256.d):00283 IORA equ $FFB1 port a data FFB2 ( f256.d):00284 DDRB equ $FFB2 port b data direction register FFB3 ( f256.d):00285 DDRA equ $FFB3 port a data direction register FFB4 ( f256.d):00286 T1C_L equ $FFB4 timer 1 counter low FFB5 ( f256.d):00287 T1C_H equ $FFB5 timer 1 counter high FFB6 ( f256.d):00288 T1L_L equ $FFB6 timer 1 latch low FFB7 ( f256.d):00289 T1L_H equ $FFB7 timer 1 latch high FFB8 ( f256.d):00290 T2C_L equ $FFB8 timer 2 counter low FFB9 ( f256.d):00291 T2C_H equ $FFB9 timer 2 counter high FFBA ( f256.d):00292 SDR equ $FFBA serial data register FFBB ( f256.d):00293 ACR equ $FFBB auxiliary control register FFBC ( f256.d):00294 PCR equ $FFBC peripheral control register FFBD ( f256.d):00295 IFR equ $FFBD interrupt flag register FFBE ( f256.d):00296 IER equ $FFBE interrupt enable register FFBF ( f256.d):00297 IORA2 equ $FFBF port a data (no handshake) ( f256.d):00298 ( f256.d):00299 * ACR control register values 00C0 ( f256.d):00300 T1_CTRL equ %11000000 0020 ( f256.d):00301 T2_CTRL equ %00100000 001C ( f256.d):00302 SR_CTRL equ %00011100 0002 ( f256.d):00303 PBL_EN equ %00000010 0001 ( f256.d):00304 PAL_EN equ %00000001 ( f256.d):00305 ( f256.d):00306 * PCR control register values 00E0 ( f256.d):00307 CB2_CTRL equ %11100000 0010 ( f256.d):00308 CB1_CTRL equ %00010000 000E ( f256.d):00309 CA2_CTRL equ %00001110 0001 ( f256.d):00310 CA1_CTRL equ %00000001 ( f256.d):00311 ( f256.d):00312 * IFR control register values 0080 ( f256.d):00313 IRQF equ %10000000 0040 ( f256.d):00314 T1F equ %01000000 0020 ( f256.d):00315 T2F equ %00100000 0010 ( f256.d):00316 CB1F equ %00010000 0008 ( f256.d):00317 CB2F equ %00001000 0004 ( f256.d):00318 SRF equ %00000100 0002 ( f256.d):00319 CA1F equ %00000010 0001 ( f256.d):00320 CA2F equ %00000001 ( f256.d):00321 ( f256.d):00322 * IER control register values 0080 ( f256.d):00323 IERSET equ %10000000 0040 ( f256.d):00324 T1E equ %01000000 0020 ( f256.d):00325 T2E equ %00100000 0010 ( f256.d):00326 CB1E equ %00010000 0008 ( f256.d):00327 CB2E equ %00001000 0004 ( f256.d):00328 SRE equ %00000100 0002 ( f256.d):00329 CA1E equ %00000010 0001 ( f256.d):00330 CA2E equ %00000001 ( f256.d):00331 ( f256.d):00332 ******************************************************************** ( f256.d):00333 * F256 real-time clock definitions ( f256.d):00334 * FE40 ( f256.d):00335 RTC.Base equ 0xFE40 0000 ( f256.d):00336 RTC_SEC equ 0x00 seconds register 0001 ( f256.d):00337 RTC_SEC_ALARM equ 0x01 seconds alarm register 0002 ( f256.d):00338 RTC_MIN equ 0x02 minutes register 0003 ( f256.d):00339 RTC_MIN_ALARM equ 0x03 minutes alarm register 0004 ( f256.d):00340 RTC_HRS equ 0x04 hours register 0005 ( f256.d):00341 RTC_HRS_ALARM equ 0x05 hours alarm register 0006 ( f256.d):00342 RTC_DAY equ 0x06 day register 0007 ( f256.d):00343 RTC_DAY_ALARM equ 0x07 day alarm register 0008 ( f256.d):00344 RTC_DOW equ 0x08 day of week register 0009 ( f256.d):00345 RTC_MONTH equ 0x09 month register 000A ( f256.d):00346 RTC_YEAR equ 0x0A year register 000B ( f256.d):00347 RTC_RATES equ 0x0B rates register 000C ( f256.d):00348 RTC_ENABLE equ 0x0C enables register 000D ( f256.d):00349 RTC_FLAGS equ 0x0D flags register 000E ( f256.d):00350 RTC_CTRL equ 0x0E control register 000F ( f256.d):00351 RTC_CENTURY equ 0x0F century register ( f256.d):00352 0002 ( f256.d):00353 RTC_24HR equ $02 12/24 hour flag (1 = 24 Hr, 0 = 12 Hr) 0004 ( f256.d):00354 RTC_STOP equ $04 0 = STOP when power off, 1 = run from battery when power off 0008 ( f256.d):00355 RTC_UTI equ $08 update transfer inhibit ( f256.d):00356 ******************************************************************** ( f256.d):00357 * F256 W65C22S definitions ( f256.d):00358 * FFB0 ( f256.d):00359 VIA_ORB_IRB equ 0xFFB0 output/input register port B FFB1 ( f256.d):00360 VIA_ORA_IRA equ 0xFFB1 output/input register port B FFB2 ( f256.d):00361 VIA_DDRB equ 0xFFB2 data direction port B FFB3 ( f256.d):00362 VIA_DDRA equ 0xFFB3 data direction port A FFB4 ( f256.d):00363 VIA_T1CL equ 0xFFB4 T1C-L FFB5 ( f256.d):00364 VIA_T1CH equ 0xFFB5 T1C-H FFB6 ( f256.d):00365 VIA_T1LL equ 0xFFB6 T1L-L FFB7 ( f256.d):00366 VIA_T1LH equ 0xFFB7 T1L-H FFB8 ( f256.d):00367 VIA_T2CL equ 0xFFB8 T2C-L FFB9 ( f256.d):00368 VIA_T2CH equ 0xFFB9 T2C-H FFBA ( f256.d):00369 VIA_SR equ 0xFFBA SR FFBB ( f256.d):00370 VIA_ACR equ 0xFFBB ACR FFBC ( f256.d):00371 VIA_PCR equ 0xFFBC PCR FFBD ( f256.d):00372 VIA_IFR equ 0xFFBD IFR FFBE ( f256.d):00373 VIA_IER equ 0xFFBE IER FFBF ( f256.d):00374 VIA_ORA_IRA_AUX equ 0xFFBF ORA/IRA ( f256.d):00375 * Definition for where the Joystick Ports are ( f256.d):00376 * Port A (Joystick Port 1) 0001 ( f256.d):00377 JOYA_UP equ 0x01 0002 ( f256.d):00378 JOYA_DWN equ 0x02 0004 ( f256.d):00379 JOYA_LFT equ 0x04 0008 ( f256.d):00380 JOTA_RGT equ 0x08 0010 ( f256.d):00381 JOTA_BUT0 equ 0x10 0020 ( f256.d):00382 JOYA_BUT1 equ 0x20 0040 ( f256.d):00383 JOYA_BUT2 equ 0x40 ( f256.d):00384 * Port B (Joystick Port 0) 0001 ( f256.d):00385 JOYB_UP equ 0x01 0002 ( f256.d):00386 JOYB_DWN equ 0x02 0004 ( f256.d):00387 JOYB_LFT equ 0x04 0008 ( f256.d):00388 JOTB_RGT equ 0x08 0010 ( f256.d):00389 JOTB_BUT0 equ 0x10 0020 ( f256.d):00390 JOYB_BUT1 equ 0x20 0040 ( f256.d):00391 JOYB_BUT2 equ 0x40 ( f256.d):00392 ( f256.d):00393 ******************************************************************** ( f256.d):00394 * F256 UART definitions ( f256.d):00395 * FE60 ( f256.d):00396 UART_TRHB equ 0xFE60 transmit/receive hold buffer FE60 ( f256.d):00397 UART_DLL equ 0xFE60 divisor latch low byte FE61 ( f256.d):00398 UART_DLH equ 0xFE61 divisor latch high byte FE61 ( f256.d):00399 UART_IER equ 0xFE61 interrupt enable register FE62 ( f256.d):00400 UART_FCR equ 0xFE62 FIFO control register FE62 ( f256.d):00401 UART_IIR equ 0xFE62 interrupt identification register FE63 ( f256.d):00402 UART_LCR equ 0xFE63 line control register FE64 ( f256.d):00403 UART_MCR equ 0xFE64 modem control register FE65 ( f256.d):00404 UART_LSR equ 0xFE65 line status register FE66 ( f256.d):00405 UART_MSR equ 0xFE66 modem status register FE67 ( f256.d):00406 UART_SR equ 0xFE67 scratch register ( f256.d):00407 ( f256.d):00408 * FCR register definitions 0000 ( f256.d):00409 FCR_RXT_5 equ 0x00 0040 ( f256.d):00410 FCR_RXT_6 equ 0x40 0080 ( f256.d):00411 FCR_RXT_7 equ 0x80 00C0 ( f256.d):00412 FCR_RXT_8 equ 0xC0 0020 ( f256.d):00413 FCR_FIFO64 equ 0x20 0004 ( f256.d):00414 FCR_TXR equ 0x04 0002 ( f256.d):00415 FCR_RXR equ 0x02 0001 ( f256.d):00416 FCR_FIFOE equ 0x01 ( f256.d):00417 ( f256.d):00418 * Interrupt Enable Flags 0020 ( f256.d):00419 UINT_LOW_POWER equ 0x20 enable low power mode (16750) 0010 ( f256.d):00420 UINT_SLEEP_MODE equ 0x10 enable sleep mode (16750) 0008 ( f256.d):00421 UINT_MODEM_STATUS equ 0x08 enable modem status interrupt 0004 ( f256.d):00422 UINT_LINE_STATUS equ 0x04 enable receiver line status interrupt 0002 ( f256.d):00423 UINT_THR_EMPTY equ 0x02 enable transmit holding register empty interrupt 0001 ( f256.d):00424 UINT_DATA_AVAIL equ 0x01 enable receive data available interrupt ( f256.d):00425 ( f256.d):00426 ; Interrupt Identification Register Codes 0080 ( f256.d):00427 IIR_FIFO_ENABLED equ 0x80 FIFO is enabled 0040 ( f256.d):00428 IIR_FIFO_NONFUNC equ 0x40 FIFO is not functioning 0020 ( f256.d):00429 IIR_FIFO_64BYTE equ 0x20 64 byte FIFO enabled (16750) 0000 ( f256.d):00430 IIR_MODEM_STATUS equ 0x00 modem status interrupt 0002 ( f256.d):00431 IIR_THR_EMPTY equ 0x02 transmit holding register empty interrupt 0004 ( f256.d):00432 IIR_DATA_AVAIL equ 0x04 data available interrupt 0006 ( f256.d):00433 IIR_LINE_STATUS equ 0x06 line status interrupt 000C ( f256.d):00434 IIR_TIMEOUT equ 0x0C time-out interrupt (16550 and later) 0001 ( f256.d):00435 IIR_INTERRUPT_PENDING equ 0x01 interrupt pending flag ( f256.d):00436 ( f256.d):00437 ; Line Control Register Codes 0080 ( f256.d):00438 LCR_DLB equ 0x80 divisor latch access bit 0060 ( f256.d):00439 LCR_SBE equ 0x60 set break enable ( f256.d):00440 0000 ( f256.d):00441 LCR_PARITY_NONE equ 0x00 parity: none 0008 ( f256.d):00442 LCR_PARITY_ODD equ 0x08 parity: odd 0018 ( f256.d):00443 LCR_PARITY_EVEN equ 0x18 parity: even 0028 ( f256.d):00444 LCR_PARITY_MARK equ 0x28 parity: mark 0038 ( f256.d):00445 LCR_PARITY_SPACE equ 0x38 parity: space ( f256.d):00446 0000 ( f256.d):00447 LCR_STOPBIT_1 equ 0x00 one stop bit 0004 ( f256.d):00448 LCR_STOPBIT_2 equ 0x04 1.5 or 2 stop bits ( f256.d):00449 0000 ( f256.d):00450 LCR_DATABITS_5 equ 0x00 data bits: 5 0001 ( f256.d):00451 LCR_DATABITS_6 equ 0x01 data bits: 6 0002 ( f256.d):00452 LCR_DATABITS_7 equ 0x02 data bits: 7 0003 ( f256.d):00453 LCR_DATABITS_8 equ 0x03 data bits: 8 ( f256.d):00454 0080 ( f256.d):00455 LSR_ERR_RECEIVE equ 0x80 error in received fifo 0040 ( f256.d):00456 LSR_XMIT_DONE equ 0x40 all data has been transmitted 0020 ( f256.d):00457 LSR_XMIT_EMPTY equ 0x20 empty transmit holding register 0010 ( f256.d):00458 LSR_BREAK_INT equ 0x10 break interrupt 0008 ( f256.d):00459 LSR_ERR_FRAME equ 0x08 framing error 0004 ( f256.d):00460 LSR_ERR_PARITY equ 0x04 parity error 0002 ( f256.d):00461 LSR_ERR_OVERRUN equ 0x02 overrun error 0001 ( f256.d):00462 LSR_DATA_AVAIL equ 0x01 data is ready in the receive buffer ( f256.d):00463 ( f256.d):00464 ****************************************************************** ( f256.d):00465 * F256 text lookup definitions ( f256.d):00466 * FF00 ( f256.d):00467 TEXT_LUT_FG equ $FF00 FF40 ( f256.d):00468 TEXT_LUT_BG equ $FF40 ( f256.d):00469 ( f256.d):00470 ******************************************************************** ( f256.d):00471 * F256 SD card interface definitions ( f256.d):00472 * FE90 ( f256.d):00473 SDC_BASE_ADDR equ $FE90 0000 ( f256.d):00474 SDC_STAT equ 0 0001 ( f256.d):00475 SDC_DATA equ 1 ( f256.d):00476 ( f256.d):00477 * SDC status bits 0080 ( f256.d):00478 SPI_BUSY equ %10000000 0002 ( f256.d):00479 SPI_CLK equ %00000010 0001 ( f256.d):00480 CS_EN equ %00000001 ( f256.d):00481 FFC0 ( f256.d):00482 MASTER_CTRL_REG_L equ $FFC0 ( f256.d):00483 ;Control Bits Fields 0001 ( f256.d):00484 Mstr_Ctrl_Text_Mode_En equ $01 enable the text mode 0002 ( f256.d):00485 Mstr_Ctrl_Text_Overlay equ $02 enable the overlay of the text mode on top of graphic mode (the background color is ignored) 0004 ( f256.d):00486 Mstr_Ctrl_Graph_Mode_En equ $04 enable the graphic mode 0008 ( f256.d):00487 Mstr_Ctrl_Bitmap_En equ $08 enable the bitmap module in Vicky 0010 ( f256.d):00488 Mstr_Ctrl_TileMap_En equ $10 enable the tile module in Vicky 0020 ( f256.d):00489 Mstr_Ctrl_Sprite_En equ $20 enable the sprite module in Vicky 0040 ( f256.d):00490 Mstr_Ctrl_GAMMA_En equ $40 this enables the gamma correction - the analog and DVI have different color values; the gamma is great to correct the difference 0080 ( f256.d):00491 Mstr_Ctrl_Disable_Vid equ $80 this will disable the scanning of the video hence giving 100% bandwidth to the CPU FFC1 ( f256.d):00492 MASTER_CTRL_REG_H equ $FFC1 0010 ( f256.d):00493 FON_SET equ %0010000 0010 ( f256.d):00494 FON_OVLY equ %00010000 0008 ( f256.d):00495 MON_SLP equ %00001000 0004 ( f256.d):00496 DBL_Y equ %00000100 0002 ( f256.d):00497 DBL_X equ %00000010 0001 ( f256.d):00498 CLK_70 equ %00000001 ( f256.d):00499 ( f256.d):00500 ; Reserved - TBD FFC2 ( f256.d):00501 VKY_RESERVED_00 equ $FFC2 FFC3 ( f256.d):00502 VKY_RESERVED_01 equ $FFC3 ( f256.d):00503 ; FFC4 ( f256.d):00504 BORDER_CTRL_REG equ $FFC4 bit[0] - enable (1 by default) bit[4..6]: X scroll offset (will scroll left) (acceptable values: 0..7) 0001 ( f256.d):00505 Border_Ctrl_Enable equ $01 FFC5 ( f256.d):00506 BORDER_COLOR_B equ $FFC5 FFC6 ( f256.d):00507 BORDER_COLOR_G equ $FFC6 FFC7 ( f256.d):00508 BORDER_COLOR_R equ $FFC7 FFC8 ( f256.d):00509 BORDER_X_SIZE equ $FFC8 X values: 0 - 32 (default: 32) FFC9 ( f256.d):00510 BORDER_Y_SIZE equ $FFC9 Y values: 0 - 32 (default: 32) ( f256.d):00511 ; Reserved - TBD FFCA ( f256.d):00512 VKY_RESERVED_02 equ $FFCA FFCB ( f256.d):00513 VKY_RESERVED_03 equ $FFCB FFCC ( f256.d):00514 VKY_RESERVED_04 equ $FFCC ( f256.d):00515 ; Valid in Graphics Mode Only FFCD ( f256.d):00516 BACKGROUND_COLOR_B equ $FFCD when in graphic mode, if a pixel is "0" then the background pixel is chosen FFCE ( f256.d):00517 BACKGROUND_COLOR_G equ $FFCE FFCF ( f256.d):00518 BACKGROUND_COLOR_R equ $FFCF ( f256.d):00519 ; Cursor Registers FFD0 ( f256.d):00520 VKY_TXT_CURSOR_CTRL_REG equ $FFD0 [0] Enable Text Mode 0001 ( f256.d):00521 Vky_Cursor_Enable equ $01 0002 ( f256.d):00522 Vky_Cursor_Flash_Rate0 equ $02 0004 ( f256.d):00523 Vky_Cursor_Flash_Rate1 equ $04 0008 ( f256.d):00524 Vky_Cursor_Flash_Disable equ $08 FFD1 ( f256.d):00525 VKY_TXT_START_ADD_PTR equ $FFD1 this is an offset to change the starting address of the text mode Buffer (in X) FFD2 ( f256.d):00526 VKY_TXT_CURSOR_CHAR_REG equ $FFD2 FFD3 ( f256.d):00527 VKY_TXT_CURSOR_COLR_REG equ $FFD3 FFD4 ( f256.d):00528 VKY_TXT_CURSOR_X_REG_L equ $FFD4 FFD5 ( f256.d):00529 VKY_TXT_CURSOR_X_REG_H equ $FFD5 FFD6 ( f256.d):00530 VKY_TXT_CURSOR_Y_REG_L equ $FFD6 FFD7 ( f256.d):00531 VKY_TXT_CURSOR_Y_REG_H equ $FFD7 ( f256.d):00532 ; Line interrupt FFD8 ( f256.d):00533 VKY_LINE_IRQ_CTRL_REG equ $FFD8 [0] - enable line 0 - write only FFD9 ( f256.d):00534 VKY_LINE_CMP_VALUE_LO equ $FFD9 write only [7:0] FFDA ( f256.d):00535 VKY_LINE_CMP_VALUE_HI equ $FFDA write only [3:0] ( f256.d):00536 FFD8 ( f256.d):00537 VKY_PIXEL_X_POS_LO equ $FFD8 this is where on the video line is the pixel FFD9 ( f256.d):00538 VKY_PIXEL_X_POS_HI equ $FFD9 or what pixel is being displayed when the register is read FFDA ( f256.d):00539 VKY_LINE_Y_POS_LO equ $FFDA this is the line value of the raster FFDB ( f256.d):00540 VKY_LINE_Y_POS_HI equ $FFDB ( f256.d):00541 ( f256.d):00542 ; Bitmap ( f256.d):00543 ;BM0 F000 ( f256.d):00544 TyVKY_BM0_CTRL_REG equ $F000 0001 ( f256.d):00545 BM0_Ctrl equ $01 enable the BM0 0002 ( f256.d):00546 BM0_LUT0 equ $02 LUT0 0004 ( f256.d):00547 BM0_LUT1 equ $04 LUT1 F001 ( f256.d):00548 TyVKY_BM0_START_ADDY_L equ $F001 F002 ( f256.d):00549 TyVKY_BM0_START_ADDY_M equ $F002 F003 ( f256.d):00550 TyVKY_BM0_START_ADDY_H equ $F003 ( f256.d):00551 ;BM1 F008 ( f256.d):00552 TyVKY_BM1_CTRL_REG equ $F008 0001 ( f256.d):00553 BM1_Ctrl equ $01 enable the BM0 0002 ( f256.d):00554 BM1_LUT0 equ $02 LUT0 0004 ( f256.d):00555 BM1_LUT1 equ $04 LUT1 F009 ( f256.d):00556 TyVKY_BM1_START_ADDY_L equ $F009 F00A ( f256.d):00557 TyVKY_BM1_START_ADDY_M equ $F00A F00B ( f256.d):00558 TyVKY_BM1_START_ADDY_H equ $F00B ( f256.d):00559 ;BM2 F010 ( f256.d):00560 TyVKY_BM2_CTRL_REG equ $F010 0001 ( f256.d):00561 BM2_Ctrl equ $01 enable the BM0 0002 ( f256.d):00562 BM2_LUT0 equ $02 LUT0 0004 ( f256.d):00563 BM2_LUT1 equ $04 LUT1 0008 ( f256.d):00564 BM2_LUT2 equ $08 LUT2 F011 ( f256.d):00565 TyVKY_BM2_START_ADDY_L equ $F011 F012 ( f256.d):00566 TyVKY_BM2_START_ADDY_M equ $F012 F013 ( f256.d):00567 TyVKY_BM2_START_ADDY_H equ $F013 ( f256.d):00568 ( f256.d):00569 ( f256.d):00570 ; Tile map F100 ( f256.d):00571 TyVKY_TL_CTRL0 equ $F100 ( f256.d):00572 ; Bit Field Definition for the Control Register 0001 ( f256.d):00573 TILE_Enable equ $01 0002 ( f256.d):00574 TILE_LUT0 equ $02 0004 ( f256.d):00575 TILE_LUT1 equ $04 0008 ( f256.d):00576 TILE_LUT2 equ $08 0010 ( f256.d):00577 TILE_SIZE equ $10 0 -> 16x16, 0 -> 8x8 ( f256.d):00578 ( f256.d):00579 ; ( f256.d):00580 ;Tile mao layer 0 registers F100 ( f256.d):00581 TL0_CONTROL_REG equ $F100 bit[0] - enable, bit[3:1] - LUT select F101 ( f256.d):00582 TL0_START_ADDY_L equ $F101 not used right now - starting address to where is the map F102 ( f256.d):00583 TL0_START_ADDY_M equ $F102 F103 ( f256.d):00584 TL0_START_ADDY_H equ $F103 F104 ( f256.d):00585 TL0_MAP_X_SIZE_L equ $F104 the size X of the map F105 ( f256.d):00586 TL0_MAP_X_SIZE_H equ $F105 F106 ( f256.d):00587 TL0_MAP_Y_SIZE_L equ $F106 the size Y of the map F107 ( f256.d):00588 TL0_MAP_Y_SIZE_H equ $F107 F108 ( f256.d):00589 TL0_MAP_X_POS_L equ $F108 the position X of the map F109 ( f256.d):00590 TL0_MAP_X_POS_H equ $F109 F10A ( f256.d):00591 TL0_MAP_Y_POS_L equ $F10A the position Y of the map F10B ( f256.d):00592 TL0_MAP_Y_POS_H equ $F10B ( f256.d):00593 ;Tile MAP Layer 1 Registers F10C ( f256.d):00594 TL1_CONTROL_REG equ $F10C bit[0] - enable, bit[3:1] - LUT select F10D ( f256.d):00595 TL1_START_ADDY_L equ $F10D not used right now - starting address to where is the map F10E ( f256.d):00596 TL1_START_ADDY_M equ $F10E F10F ( f256.d):00597 TL1_START_ADDY_H equ $F10F F110 ( f256.d):00598 TL1_MAP_X_SIZE_L equ $F110 the size X of the map F111 ( f256.d):00599 TL1_MAP_X_SIZE_H equ $F111 F112 ( f256.d):00600 TL1_MAP_Y_SIZE_L equ $F112 the size Y of the map F113 ( f256.d):00601 TL1_MAP_Y_SIZE_H equ $F113 F114 ( f256.d):00602 TL1_MAP_X_POS_L equ $F114 the position X of the map F115 ( f256.d):00603 TL1_MAP_X_POS_H equ $F115 F116 ( f256.d):00604 TL1_MAP_Y_POS_L equ $F116 the position Y of the map F117 ( f256.d):00605 TL1_MAP_Y_POS_H equ $F117 ( f256.d):00606 ;Tile MAP Layer 2 Registers F118 ( f256.d):00607 TL2_CONTROL_REG equ $F118 bit[0] - enable, bit[3:1] - LUT select, F119 ( f256.d):00608 TL2_START_ADDY_L equ $F119 not used right now - starting address to where is the map F11A ( f256.d):00609 TL2_START_ADDY_M equ $F11A F11B ( f256.d):00610 TL2_START_ADDY_H equ $F11B F11C ( f256.d):00611 TL2_MAP_X_SIZE_L equ $F11C the size X of the map F11D ( f256.d):00612 TL2_MAP_X_SIZE_H equ $F11D F11E ( f256.d):00613 TL2_MAP_Y_SIZE_L equ $F11E the size Y of the map F11F ( f256.d):00614 TL2_MAP_Y_SIZE_H equ $F11F F120 ( f256.d):00615 TL2_MAP_X_POS_L equ $F120 the position X of the map F121 ( f256.d):00616 TL2_MAP_X_POS_H equ $F121 F122 ( f256.d):00617 TL2_MAP_Y_POS_L equ $F122 the position Y of the map F123 ( f256.d):00618 TL2_MAP_Y_POS_H equ $F123 ( f256.d):00619 ( f256.d):00620 F180 ( f256.d):00621 TILE_MAP_ADDY0_L equ $F180 F181 ( f256.d):00622 TILE_MAP_ADDY0_M equ $F181 F182 ( f256.d):00623 TILE_MAP_ADDY0_H equ $F182 F183 ( f256.d):00624 TILE_MAP_ADDY0_CFG equ $F183 F184 ( f256.d):00625 TILE_MAP_ADDY1 equ $F184 F188 ( f256.d):00626 TILE_MAP_ADDY2 equ $F188 F18C ( f256.d):00627 TILE_MAP_ADDY3 equ $F18C F190 ( f256.d):00628 TILE_MAP_ADDY4 equ $F190 F194 ( f256.d):00629 TILE_MAP_ADDY5 equ $F194 F198 ( f256.d):00630 TILE_MAP_ADDY6 equ $F198 F19C ( f256.d):00631 TILE_MAP_ADDY7 equ $F19C ( f256.d):00632 ( f256.d):00633 D300 ( f256.d):00634 XYMATH_CTRL_REG equ $D300 reserved D301 ( f256.d):00635 XYMATH_ADDY_L equ $D301 w D302 ( f256.d):00636 XYMATH_ADDY_M equ $D302 w D303 ( f256.d):00637 XYMATH_ADDY_H equ $D303 w D304 ( f256.d):00638 XYMATH_ADDY_POSX_L equ $D304 r/w D305 ( f256.d):00639 XYMATH_ADDY_POSX_H equ $D305 r/w D306 ( f256.d):00640 XYMATH_ADDY_POSY_L equ $D306 r/w D307 ( f256.d):00641 XYMATH_ADDY_POSY_H equ $D307 r/w D308 ( f256.d):00642 XYMATH_BLOCK_OFF_L equ $D308 r only - low block offset D309 ( f256.d):00643 XYMATH_BLOCK_OFF_H equ $D309 r only - hi block offset D30A ( f256.d):00644 XYMATH_MMU_BLOCK equ $D30A r only - which mmu block D30B ( f256.d):00645 XYMATH_ABS_ADDY_L equ $D30B low absolute results D30C ( f256.d):00646 XYMATH_ABS_ADDY_M equ $D30C mid absolute results D30D ( f256.d):00647 XYMATH_ABS_ADDY_H equ $D30D hi absolute results ( f256.d):00648 ( f256.d):00649 ; Sprite block0 0001 ( f256.d):00650 SPRITE_Ctrl_Enable equ $01 0002 ( f256.d):00651 SPRITE_LUT0 equ $02 0004 ( f256.d):00652 SPRITE_LUT1 equ $04 0008 ( f256.d):00653 SPRITE_DEPTH0 equ $08 00 = total front - 01 = in between l0 and l1, 10 = in between l1 and l2, 11 = total back 0010 ( f256.d):00654 SPRITE_DEPTH1 equ $10 0020 ( f256.d):00655 SPRITE_SIZE0 equ $20 00 = 32x32 - 01 = 24x24 - 10 = 16x16 - 11 = 8x8 0040 ( f256.d):00656 SPRITE_SIZE1 equ $40 ( f256.d):00657 ( f256.d):00658 F300 ( f256.d):00659 SP0_Ctrl equ $F300 F301 ( f256.d):00660 SP0_Addy_L equ $F301 F302 ( f256.d):00661 SP0_Addy_M equ $F302 F303 ( f256.d):00662 SP0_Addy_H equ $F303 F304 ( f256.d):00663 SP0_X_L equ $F304 F305 ( f256.d):00664 SP0_X_H equ $F305 F306 ( f256.d):00665 SP0_Y_L equ $F306 in the Jr, only the l is used (200 & 240) F307 ( f256.d):00666 SP0_Y_H equ $F307 always keep @ zero '0' because in Vicky the value is still considered a 16bits value ( f256.d):00667 F308 ( f256.d):00668 SP1_Ctrl equ $F308 F309 ( f256.d):00669 SP1_Addy_L equ $F309 F30A ( f256.d):00670 SP1_Addy_M equ $F30A F30B ( f256.d):00671 SP1_Addy_H equ $F30B F30C ( f256.d):00672 SP1_X_L equ $F30C F30D ( f256.d):00673 SP1_X_H equ $F30D F30E ( f256.d):00674 SP1_Y_L equ $F30E in the Jr, only the l is used (200 & 240) F30F ( f256.d):00675 SP1_Y_H equ $F30F always keep @ zero '0' because in Vicky the value is still considered a 16bits value ( f256.d):00676 F310 ( f256.d):00677 SP2_Ctrl equ $F310 F311 ( f256.d):00678 SP2_Addy_L equ $F311 F312 ( f256.d):00679 SP2_Addy_M equ $F312 F313 ( f256.d):00680 SP2_Addy_H equ $F313 F314 ( f256.d):00681 SP2_X_L equ $F314 F315 ( f256.d):00682 SP2_X_H equ $F315 F316 ( f256.d):00683 SP2_Y_L equ $F316 in the Jr, only the l is used (200 & 240) F317 ( f256.d):00684 SP2_Y_H equ $F317 always keep @ zero '0' because in Vicky the value is still considered a 16bits value ( f256.d):00685 F318 ( f256.d):00686 SP3_Ctrl equ $F318 F319 ( f256.d):00687 SP3_Addy_L equ $F319 F31A ( f256.d):00688 SP3_Addy_M equ $F31A F31B ( f256.d):00689 SP3_Addy_H equ $F31B F31C ( f256.d):00690 SP3_X_L equ $F31C F31D ( f256.d):00691 SP3_X_H equ $F31D F31E ( f256.d):00692 SP3_Y_L equ $F31E in the Jr, only the l is used (200 & 240) F31F ( f256.d):00693 SP3_Y_H equ $F31F always keep @ zero '0' because in Vicky the value is still considered a 16bits value ( f256.d):00694 F320 ( f256.d):00695 SP4_Ctrl equ $F320 F321 ( f256.d):00696 SP4_Addy_L equ $F321 F322 ( f256.d):00697 SP4_Addy_M equ $F322 F323 ( f256.d):00698 SP4_Addy_H equ $F323 F324 ( f256.d):00699 SP4_X_L equ $F324 F325 ( f256.d):00700 SP4_X_H equ $F325 F326 ( f256.d):00701 SP4_Y_L equ $F326 in the Jr, only the l is used (200 & 240) F327 ( f256.d):00702 SP4_Y_H equ $F327 always keep @ zero '0' because in Vicky the value is still considered a 16bits value ( f256.d):00703 ( f256.d):00704 ( f256.d):00705 ( f256.d):00706 ( f256.d):00707 ; PAGE $C1 E800 ( f256.d):00708 TyVKY_LUT0 equ $E800 -$d000 - $d3ff EC00 ( f256.d):00709 TyVKY_LUT1 equ $EC00 -$d400 - $d7ff F000 ( f256.d):00710 TyVKY_LUT2 equ $F000 -$d800 - $dbff F400 ( f256.d):00711 TyVKY_LUT3 equ $F400 -$dc00 - $dfff ( f256.d):00712 ( f256.d):00713 ( f256.d):00714 ;DMA FEE0 ( f256.d):00715 DMA_CTRL_REG equ $FEE0 0001 ( f256.d):00716 DMA_CTRL_Enable equ $01 0002 ( f256.d):00717 DMA_CTRL_1D_2D equ $02 0004 ( f256.d):00718 DMA_CTRL_Fill equ $04 0008 ( f256.d):00719 DMA_CTRL_Int_En equ $08 0010 ( f256.d):00720 DMA_CTRL_NotUsed0 equ $10 0020 ( f256.d):00721 DMA_CTRL_NotUsed1 equ $20 0040 ( f256.d):00722 DMA_CTRL_NotUsed2 equ $40 0080 ( f256.d):00723 DMA_CTRL_Start_Trf equ $80 ( f256.d):00724 FEE1 ( f256.d):00725 DMA_DATA_2_WRITE equ $FEE1 write only FEE1 ( f256.d):00726 DMA_STATUS_REG equ $FEE1 read only 0080 ( f256.d):00727 DMA_STATUS_TRF_IP equ $80 transfer in progress FEE2 ( f256.d):00728 DMA_RESERVED_0 equ $FEE2 FEE3 ( f256.d):00729 DMA_RESERVED_1 equ $FEE3 ( f256.d):00730 ( f256.d):00731 ; Source addy FEE4 ( f256.d):00732 DMA_SOURCE_ADDY_L equ $FEE4 FEE5 ( f256.d):00733 DMA_SOURCE_ADDY_M equ $FEE5 FEE6 ( f256.d):00734 DMA_SOURCE_ADDY_H equ $FEE6 FEE7 ( f256.d):00735 DMA_RESERVED_2 equ $FEE7 ( f256.d):00736 ; Destination Addy FEE8 ( f256.d):00737 DMA_DEST_ADDY_L equ $FEE8 FEE9 ( f256.d):00738 DMA_DEST_ADDY_M equ $FEE9 FEEA ( f256.d):00739 DMA_DEST_ADDY_H equ $FEEA FEEB ( f256.d):00740 DMA_RESERVED_3 equ $FEEB ( f256.d):00741 ; Size in 1D Mode FEEC ( f256.d):00742 DMA_SIZE_1D_L equ $FEEC FEED ( f256.d):00743 DMA_SIZE_1D_M equ $FEED FEEE ( f256.d):00744 DMA_SIZE_1D_H equ $FEEE FEEF ( f256.d):00745 DMA_RESERVED_4 equ $FEEF ( f256.d):00746 ; Size in 2D Mode FEEC ( f256.d):00747 DMA_SIZE_X_L equ $FEEC FEED ( f256.d):00748 DMA_SIZE_X_H equ $FEED FEEE ( f256.d):00749 DMA_SIZE_Y_L equ $FEEE FEEF ( f256.d):00750 DMA_SIZE_Y_H equ $FEEF ( f256.d):00751 ; Stride in 2D Mode FEF0 ( f256.d):00752 DMA_SRC_STRIDE_X_L equ $FEF0 FEF1 ( f256.d):00753 DMA_SRC_STRIDE_X_H equ $FEF1 FEF2 ( f256.d):00754 DMA_DST_STRIDE_Y_L equ $FEF2 FEF3 ( f256.d):00755 DMA_DST_STRIDE_Y_H equ $FEF3 ( f256.d):00756 FEF4 ( f256.d):00757 DMA_RESERVED_5 equ $FEF4 FEF5 ( f256.d):00758 DMA_RESERVED_6 equ $FEF5 FEF6 ( f256.d):00759 DMA_RESERVED_7 equ $FEF6 FEF7 ( f256.d):00760 DMA_RESERVED_8 equ $FEF7 ( f256.d):00761 endc ( defs.d):00028 ( defs.d):00029 * F256 Jr. mapped I/O boundaries FE00 ( defs.d):00030 MappedIOStart equ $FE00 FFFF ( defs.d):00031 MappedIOEnd equ $FFFF ( defs.d):00032 ( defs.d):00033 * F256 Jr. ticks per second support 003C ( defs.d):00034 TkPerSec set 60 ( go2.asm):00019 0011 ( go2.asm):00020 tylg set Prgrm+Objct 0081 ( go2.asm):00021 atrv set ReEnt+rev 0001 ( go2.asm):00022 rev set $01 0001 ( go2.asm):00023 edition set 1 ( go2.asm):00024 0000 87CD0042000D1181 ( go2.asm):00025 mod eom,name,tylg,atrv,start,size 6A001100C8 ( go2.asm):00026 ( go2.asm):00027 org 0 0000. ( go2.asm):00028 stack rmb 200 00C8 ( go2.asm):00029 size equ . ( go2.asm):00030 000D 676FB2 ( go2.asm):00031 name fcs /go2/ 0010 01 ( go2.asm):00032 fcb edition ( go2.asm):00033 0011 ( go2.asm):00034 start equ * ( go2.asm):00035 ( go2.asm):00036 0011 3401 ( go2.asm):00037 pshs cc 0013 1A50 ( go2.asm):00038 orcc #IntMasks 0015 86C2 ( go2.asm):00039 lda #$C2 0017 B7FFA9 ( go2.asm):00040 sta >MMU_SLOT_1 001A CC5475 ( go2.asm):00041 ldd #'T*256+'u 001D FD2000 ( go2.asm):00042 std $2000 0020 CC7262 ( go2.asm):00043 ldd #'r*256+'b 0023 FD2002 ( go2.asm):00044 std $2002 0026 CC4F53 ( go2.asm):00045 ldd #'O*256+'S 0029 FD2004 ( go2.asm):00046 std $2004 002C 3501 ( go2.asm):00047 puls cc ( go2.asm):00048 002E 3401 ( go2.asm):00049 loop@ pshs cc 0030 1A50 ( go2.asm):00050 orcc #IntMasks 0032 7C2000 ( go2.asm):00051 inc $2000 0035 3501 ( go2.asm):00052 puls cc 0037 8E0010 ( go2.asm):00053 ldx #$10 003A 103F0A ( go2.asm):00054 os9 F$Sleep 003D 20EF ( go2.asm):00055 bra loop@ ( go2.asm):00056 003F 74F830 ( go2.asm):00057 emod 0042 ( go2.asm):00058 eom equ * ( go2.asm):00059 end